In recent years, technologies for fabricating electronic devices such as semiconductor devices having device patterns with high degrees of miniaturization and integration have been further advanced. With the increased degrees of miniaturization and integration of device patterns, criteria for verifying pattern placement in device manufacturing have become more stringent. In order to improve dimensional precision of device patterns, optical proximity correction (OPC) techniques have been developed. OPC is a correction technique in which an edge of an original design layout pattern is moved so that a device pattern having desired dimensions may be formed on a substrate.
In pattern verification in general, patterns in an original design layout are corrected by OPC so that pattern data is obtained. Then, contour plots are created by lithography simulation using the pattern data, and defects included in the contour plots are verified. The contour plots with defects detected by a lithography simulator (hereinafter referred to as “defective contour plots”) are sorted in accordance with the types of defects, using pattern matching for example. Then, pattern verification is performed on the defective contour plots.
Along with the increases in degrees of miniaturization and integration of device patterns, there are more cases where OPC-processed patterns have complex shapes. As a result, the matching ratio in pattern matching in classifying of defective contour plots decreases, and consequently, precise pattern verification requires a significant number of processes and a significant length of time.